UM  > 微電子研究院
A 36-Gb/s 1.3-mW/Gb/s duobinary-signal transmitter exploiting power-efficient cross-quadrature clocking multiplexers with maximized timing margin
Chen Y.1; Mak P.-I.1; Boon C.C.3; Martins R.P.1
2018-09-01
Source PublicationIEEE Transactions on Circuits and Systems I: Regular Papers
ISSN15498328
Volume65Issue:9Pages:3014-3026
Abstract

For wireline transmitters delivering a high-speed multi-level signal, such as pulse-amplitude-modulation-4 or duobinary, a high-performance multiplexer (MUX) is critical to serialize the low-speed parallel data into one full-speed output. To enhance the power efficiency and data eye's opening, this paper proposes a universal 2-to-1 MUX, featuring a cross-quadrature clocking technique to enlarge the timing margin, and a simplified three-latch topology without delay buffers to boost the internal bandwidth (BW). The MUX ratios are extendable to 4-to-2 and 4-to-1, and their benefits are exemplified via a duobinary-signal transmitter. It further includes an output driver unifying the MUX-and-SUM operation, a BW-extended single-to-differential converter, and an active-inductor-embedded clock buffer for swing enhancement. Also, a predictive method for estimating the duobinary-signal data-dependent jitter according to the load capacitance of the output driver is developed. Fabricated in 65-nm CMOS, the transmitter exhibits a figure-of-merit of 1.3 mW/Gb/s at 36 Gb/s, while occupying a compact die area of 0.037 mm.

KeywordBandwidth (Bw) Cmos Cross-quadrature Clocking D-type Flip-flop (Dff) Data-dependent Jitter (Ddj) Duobinary Figure-of-merit (Fom) Latch Multi-level Signaling Multiplexer (Mux) Selector Timing Margin
DOIhttp://doi.org/10.1109/TCSI.2018.2829725
URLView the original
Indexed BySCI
Language英语
WOS Research AreaEngineering
WOS SubjectEngineering, Electrical & Electronic
WOS IDWOS:000440852500033
Fulltext Access
Citation statistics
Cited Times [WOS]:1   [WOS Record]     [Related Records in WOS]
Document TypeJournal article
CollectionINSTITUTE OF MICROELECTRONICS
DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
Affiliation1.Universidade de Macau
2.Instituto Superior Técnico
3.Nanyang Technological University
Recommended Citation
GB/T 7714
Chen Y.,Mak P.-I.,Boon C.C.,et al. A 36-Gb/s 1.3-mW/Gb/s duobinary-signal transmitter exploiting power-efficient cross-quadrature clocking multiplexers with maximized timing margin[J]. IEEE Transactions on Circuits and Systems I: Regular Papers,2018,65(9):3014-3026.
APA Chen Y.,Mak P.-I.,Boon C.C.,&Martins R.P..(2018).A 36-Gb/s 1.3-mW/Gb/s duobinary-signal transmitter exploiting power-efficient cross-quadrature clocking multiplexers with maximized timing margin.IEEE Transactions on Circuits and Systems I: Regular Papers,65(9),3014-3026.
MLA Chen Y.,et al."A 36-Gb/s 1.3-mW/Gb/s duobinary-signal transmitter exploiting power-efficient cross-quadrature clocking multiplexers with maximized timing margin".IEEE Transactions on Circuits and Systems I: Regular Papers 65.9(2018):3014-3026.
Related Services
Recommend this item
Bookmark
Usage statistics
Export to Endnote
Google Scholar
Similar articles in Google Scholar
[Chen Y.]'s Articles
[Mak P.-I.]'s Articles
[Boon C.C.]'s Articles
Baidu academic
Similar articles in Baidu academic
[Chen Y.]'s Articles
[Mak P.-I.]'s Articles
[Boon C.C.]'s Articles
Bing Scholar
Similar articles in Bing Scholar
[Chen Y.]'s Articles
[Mak P.-I.]'s Articles
[Boon C.C.]'s Articles
Terms of Use
No data!
Social Bookmark/Share
All comments (0)
No comment.
 

Items in the repository are protected by copyright, with all rights reserved, unless otherwise indicated.