A hardware-efficient feedback polynomial topology for dpd linearization of power amplifiers: Theory and FPGA validation
Cheang C.-F.2; Mak P.-I.2; Martins R.P.2
2018-09-01
Source PublicationIEEE Transactions on Circuits and Systems I: Regular Papers
ISSN15498328
Volume65Issue:9Pages:2889-2902
Abstract

This paper describes a hardware-efficient feedback polynomial topology for digital predistortion (DPD) linearization of power amplifiers. Unlike the existing pruned Volterra-series DPD linearization that compensates the nonlinearities in parallel, our topology tailors a feedback memory block, such that the nonlinearities and memory effects can be constructed separately, minimizing the running complexity while significantly reducing the size of the coefficients extractor. Yet, the coefficients of the feedback memory block cannot be extracted in the direct form. To surmount it, a design methodology is developed with the aid of complexity-reduced Volterra-series model. Also, it is known that the least square estimation can extract the coefficients of the digital predistorter, but its pseudo-inverse operation between the inputs and outputs involves heavy matrix multiplications and division. With a computational complexity of O(N), the coefficients extractor could hardly be implemented efficiently in the field-programmable gate array (FPGA). Here, we propose a division-free line-searched-based recursive least square algorithm for adaptive linear and nonlinear coefficient estimation, relaxing the computational complexity to O(N) and supporting adaptive estimation in the FPGA. Our DPD experiments demonstrate both identification and predistortion procedures fully implemented in the FPGA. The measured error vector magnitude is reduced from 10.1% to <3.2%, and the adjacent channel leakage ratio (ACLR) is improved from -28.4 to -46.1 dBc, for a 20-MHz 64-QAM orthogonal frequency division multiplexing signal. For carrier-aggregation signals, the ACLR is improved from -35.8 to -45.3 dBc.

KeywordCarrier-aggregation Digital Predistortion (Dpd) Field-programmable Gate Array (Fpga) Identification Power Amplifier (Pa) Recursive Least Square (Rls)
DOIhttp://doi.org/10.1109/TCSI.2017.2788082
URLView the original
Indexed BySCI
Language英语
WOS Research AreaEngineering
WOS SubjectEngineering, Electrical & Electronic
WOS IDWOS:000440852500022
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Cited Times [WOS]:6   [WOS Record]     [Related Records in WOS]
Document TypeJournal article
CollectionDEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
Corresponding AuthorMak P.-I.; Martins R.P.
Affiliation1.Instituto Superior Técnico
2.Universidade de Macau
Recommended Citation
GB/T 7714
Cheang C.-F.,Mak P.-I.,Martins R.P.. A hardware-efficient feedback polynomial topology for dpd linearization of power amplifiers: Theory and FPGA validation[J]. IEEE Transactions on Circuits and Systems I: Regular Papers,2018,65(9):2889-2902.
APA Cheang C.-F.,Mak P.-I.,&Martins R.P..(2018).A hardware-efficient feedback polynomial topology for dpd linearization of power amplifiers: Theory and FPGA validation.IEEE Transactions on Circuits and Systems I: Regular Papers,65(9),2889-2902.
MLA Cheang C.-F.,et al."A hardware-efficient feedback polynomial topology for dpd linearization of power amplifiers: Theory and FPGA validation".IEEE Transactions on Circuits and Systems I: Regular Papers 65.9(2018):2889-2902.
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