UM
A 2-GS/s 8-Bit ADC Featuring Virtual-Ground Sampling Interleaved Architecture in 28-nm CMOS
Wang, X. Shawn1; Jin, Xin2; Du, Jieqiong1; Li, Yilei1; Du, Yuan1; Wong, Chien-Heng1; Kuan, Yen-Cheng3; Chan, Chi-Hang4; Chang, Mau-Chung Frank1,5
2018-11
Source PublicationIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
ISSN1549-7747
Volume65Issue:11Pages:1534-1538
AbstractThis brief presents a two-way time-interleaved twostep pipelined analog-to-digital converter (ADC) architecture built upon a new concept of virtual-ground sampling, featuring merged front-end track-and-hold, residue generation, input termination, and buffering. This architecture is investigated to alleviate the front-end performance tradeoff among the total-harmonic- distortion, bandwidth, and sampling rate (interleaving factor). A 2-GS/s 8b ADC using the new architecture was designed and fabricated in 28-nm CMOS, achieving 43-dB SNDR and 55-dB SFDR up to Nyquist frequency.
KeywordAnalog-to-digital converter (ADC) virtual-ground sampling SAR time-interleaved
DOI10.1109/TCSII.2017.2758323
URLView the original
Indexed BySCI
Language英语
WOS Research AreaEngineering
WOS SubjectEngineering, Electrical & Electronic
WOS IDWOS:000448935400009
PublisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
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Citation statistics
Cited Times [WOS]:3   [WOS Record]     [Related Records in WOS]
Document TypeJournal article
CollectionUniversity of Macau
Affiliation1.Univ Calif Los Angeles, High Speed Elect Lab, Los Angeles, CA 90095 USA;
2.Broadcom Ltd, Irvine, CA 92617 USA;
3.Natl Chiao Tung Univ, Int Coll Semicond Technol, Hsinchu 30010, Taiwan;
4.Univ Macau, State Key Lab Analog & Mixed Signal VLSI, Dept Elect & Comp Engn, Macau 999078, Peoples R China;
5.Natl Chiao Tung Univ, Dept Elect Engn, Hsinchu 30010, Taiwan
Recommended Citation
GB/T 7714
Wang, X. Shawn,Jin, Xin,Du, Jieqiong,et al. A 2-GS/s 8-Bit ADC Featuring Virtual-Ground Sampling Interleaved Architecture in 28-nm CMOS[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS,2018,65(11):1534-1538.
APA Wang, X. Shawn.,Jin, Xin.,Du, Jieqiong.,Li, Yilei.,Du, Yuan.,...&Chang, Mau-Chung Frank.(2018).A 2-GS/s 8-Bit ADC Featuring Virtual-Ground Sampling Interleaved Architecture in 28-nm CMOS.IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS,65(11),1534-1538.
MLA Wang, X. Shawn,et al."A 2-GS/s 8-Bit ADC Featuring Virtual-Ground Sampling Interleaved Architecture in 28-nm CMOS".IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 65.11(2018):1534-1538.
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