UM
Gain Error Calibrations for Two-Step ADCs: Optimizations Either in Accuracy or Chip Area
Wang, Guan Cheng1; Zhu, Yan1; Chan, Chi-Hang1; Seng-Pan, U.1,2,3; Martins, Rui P.1,2
2018-11
Source PublicationIEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
ISSN1063-8210
Volume26Issue:11Pages:2279-2289
AbstractThis paper presents two calibration schemes to correct the stage gain error in analog-to-digital converters. The two approaches target different scenarios, either better calibration accuracy or less digital overhead. First, we optimize the gain calculation scheme in the conventional code statistics-based approach, which improves the calibration accuracy. Moreover, we introduce a missing-code-detected calibration that replaces the calculation of the gain coefficient by counting and multiplying the number of missing codes in the digital domain, which significantly simplifies the digital implementation. To eliminate the calibration dependence on the input signal, we implement a testing signal generation on-chip. We also compare these calibration schemes with the requirements of the input signal, the calibration accuracy, as well as the hardware overhead based on a mathematical model with behavior simulations. Both concepts were verified in an 11-bit 80-MS/s successive approximation register with a bridge digital-to-analog converter fabricated in a 65-nm CMOS.
KeywordBridge digital-to-analog converter (DAC) gain error calibration successive approximation register (SAR) analog-to-digital converters (ADCs) testing signal generation (TSG)
DOI10.1109/TVLSI.2018.2865595
URLView the original
Indexed BySCI
Language英语
WOS Research AreaComputer Science ; Engineering
WOS SubjectComputer Science, Hardware & Architecture ; Engineering, Electrical & Electronic
WOS IDWOS:000448911900008
PublisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
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Document TypeJournal article
CollectionUniversity of Macau
Affiliation1.Univ Macau, State Key Lab Analog & Mixed Signal VLSI, Macau 999078, Peoples R China;
2.Univ Macau, Dept Elect & Comp Engn, Fac Sci & Technol, Macau 999078, Peoples R China;
3.Synopsys Macau Ltd, Macau 999078, Peoples R China
First Author AffilicationUniversity of Macau
Recommended Citation
GB/T 7714
Wang, Guan Cheng,Zhu, Yan,Chan, Chi-Hang,et al. Gain Error Calibrations for Two-Step ADCs: Optimizations Either in Accuracy or Chip Area[J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS,2018,26(11):2279-2289.
APA Wang, Guan Cheng,Zhu, Yan,Chan, Chi-Hang,Seng-Pan, U.,&Martins, Rui P..(2018).Gain Error Calibrations for Two-Step ADCs: Optimizations Either in Accuracy or Chip Area.IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS,26(11),2279-2289.
MLA Wang, Guan Cheng,et al."Gain Error Calibrations for Two-Step ADCs: Optimizations Either in Accuracy or Chip Area".IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 26.11(2018):2279-2289.
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