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Algorithmic Voltage-Feed-In Topology for Fully Integrated Fine-Grained Rational Buck-Boost Switched-Capacitor DC-DC Converters
Jiang, Yang1,2; Law, Man-Kay1; Mak, Pui-In1,2; Martins, Rui P.1,2
2018-12
Source PublicationIEEE JOURNAL OF SOLID-STATE CIRCUITS
ISSN0018-9200
Volume53Issue:12Pages:3455-3469
AbstractWe propose an algorithmic voltage-feed-in (AVFI) topology capable of systematic generation of any arbitrary buck-boost rational ratio with optimal conduction loss while achieving reduced topology-level parasitic loss among the state-of-the-art works. By disengaging the existing topology-level restrictions, we develop a cell-level implementation using the extracted Dick-son cell (DSC) and charge-path-folding cell (QFC) to minimize the power-stage parasitic loss, exhibiting a Dickson-like switching pattern. The proposed partitionable main cell (MC) and auxiliary cell (AC) architecture achieves fined-grained voltage conversion ratio (FVCR) reconfiguration with optimal power cell utilization and reduced control complexity. Implemented in 65-nm bulk CMOS, the fully integrated switched-capacitor power converter (SCPC) using 10 MCs and 10 ACs executes a total of 24 VCRs (11 buck and 13 boost) with wide-range efficient buck-boost operations through the proposed reference-selective bootstrapping driver (RSBD). Based on the AVFI topology, the chip prototype reaches a measured peak efficiency of 84.1% at a power density of 13.4 mW/mm(2) over a wide range of input (0.22-2.4 V) and output (0.85-1.2 V).
KeywordAlgorithmic voltage-feed-in (AVFI) topology buck-boost dc-dc linear topology parasitic loss power density rational voltage conversion ratio reconfigurable reference-selective bootstrapping switched capacitor
DOI10.1109/JSSC.2018.2866929
URLView the original
Indexed BySCI
Language英语
WOS Research AreaEngineering
WOS SubjectEngineering, Electrical & Electronic
WOS IDWOS:000454108600012
PublisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
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Citation statistics
Cited Times [WOS]:1   [WOS Record]     [Related Records in WOS]
Document TypeJournal article
CollectionDEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
Affiliation1.Univ Macau, State Key Lab Analog & Mixed Signal VLSI, Macau 999078, Peoples R China;
2.Univ Macau, FST ECE, Macau 999078, Peoples R China
First Author AffilicationUniversity of Macau
Recommended Citation
GB/T 7714
Jiang, Yang,Law, Man-Kay,Mak, Pui-In,et al. Algorithmic Voltage-Feed-In Topology for Fully Integrated Fine-Grained Rational Buck-Boost Switched-Capacitor DC-DC Converters[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS,2018,53(12):3455-3469.
APA Jiang, Yang,Law, Man-Kay,Mak, Pui-In,&Martins, Rui P..(2018).Algorithmic Voltage-Feed-In Topology for Fully Integrated Fine-Grained Rational Buck-Boost Switched-Capacitor DC-DC Converters.IEEE JOURNAL OF SOLID-STATE CIRCUITS,53(12),3455-3469.
MLA Jiang, Yang,et al."Algorithmic Voltage-Feed-In Topology for Fully Integrated Fine-Grained Rational Buck-Boost Switched-Capacitor DC-DC Converters".IEEE JOURNAL OF SOLID-STATE CIRCUITS 53.12(2018):3455-3469.
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