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Analysis of Reference Error in High-Speed SAR ADCs With Capacitive DAC
Li, Cheng1; Chan, Chi-Hang1; Zhu, Yan1; Martins, Rui P.1,2
2019-01
Source PublicationIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
ISSN1549-8328
Volume66Issue:1Pages:82-93
AbstractThe high-speed successive-approximation-register (SAR) analog-to-digital converters (ADCs) rely on the switched capacitive digital-to-analog converter (CDAC) to perform the fast transition, which causes voltage ripples at the output of the reference circuits. Such ripples lead to the reference error that eventually prolongs the time for DAC settling. To minimize such error with a short available time, it either demands a power-hungry reference buffer or large die area for the decoupling. In this paper, we offer a comprehensive analysis of the reference errors in SAR ADCs with a practical reference network circuit (RNC) in consideration. A circuit model is developed in order to quantify the error amplitude for the critical DAC settling condition. Based on the proposed model, the settling behavior of the DAC with reference buffer can be precisely characterized, leading to a better understanding about the design tradeoff of the RNC. Finally, the developed model is verified by both circuit level simulations and measurement results.
KeywordReference error reference buffer successive-approximation-register (SAR) analog-to-digital converter (ADC) reference ripple
DOI10.1109/TCSI.2018.2861835
URLView the original
Indexed BySCI
Language英语
WOS Research AreaEngineering
WOS SubjectEngineering, Electrical & Electronic
WOS IDWOS:000452625900007
PublisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
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Citation statistics
Cited Times [WOS]:1   [WOS Record]     [Related Records in WOS]
Document TypeJournal article
CollectionUniversity of Macau
Affiliation1.Univ Macau, State Key Lab Analog & Mixed Signal VLSI, Macau 999078, Peoples R China;
2.Univ Macau, Fac Sci & Technol, Dept Elect & Comp Engn, Macau 999078, Peoples R China
First Author AffilicationUniversity of Macau
Recommended Citation
GB/T 7714
Li, Cheng,Chan, Chi-Hang,Zhu, Yan,et al. Analysis of Reference Error in High-Speed SAR ADCs With Capacitive DAC[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS,2019,66(1):82-93.
APA Li, Cheng,Chan, Chi-Hang,Zhu, Yan,&Martins, Rui P..(2019).Analysis of Reference Error in High-Speed SAR ADCs With Capacitive DAC.IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS,66(1),82-93.
MLA Li, Cheng,et al."Analysis of Reference Error in High-Speed SAR ADCs With Capacitive DAC".IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 66.1(2019):82-93.
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